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RT8868A ? ds8868a-00 may 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. 4/3/2/1-phase pwm controller for amd am2/am2+/am3 cpus general description the RT8868A is a 4/3/2/1-phase synchronous buck controller with two integrated mosfet drivers for cpu power application and a single-phase buck with integrated mosfet driver for north-bridge (nb) chipset. the RT8868A uses differential inductor dcr current sense to achieve phase current balance and active voltage positioning. other features include adjustable operating frequency, power good indication, external error-amp compensation, over voltage protection, over current protection and enable/shutdown for various applications. the RT8868A comes in a small footprint with wqfn-48l 7x7 package. features z z z z z 12v power supply voltage z z z z z 4/3/2/1-phase power conversion for v core power z z z z z 3 embedded mosfet drivers (2 for cpu and 1 for nb) z z z z z internal regulated 5v output z z z z z support amd am2 6-bit parallel and am2+ 7-bit serial vid tables z z z z z support 3.4mhz high speed i 2 c z z z z z continuous differential inductor dcr current sense z z z z z adjustable frequency (typically at 300khz) z z z z z selectable 1 or 2 phase in power-saving (ps) mode z z z z z phase-interleaving for v core controller z z z z z power good indication z z z z z adjustable over current protection z z z z z over voltage protection z z z z z small 48-lead wqfn package z z z z z rohs compliant and halogen free applications z desktop cpu core power z low voltage, high current dc/dc converter pin configurations wqfn-48l 7x7 imax_nb imax isn1 isp1 isn2 isp2 vcc5 isn3 isp3 isn4 isp4 ps en pgood vid5 vid4 vid3/svc vid2/svd ugate_nb vid1/pvi vid0/vfixen vcc12_nb lgate_nb phase_nb boot_nb phase1 ugate1 pwm4 pwm3 boot2 ugate2 phase2 lgate2 lgate1 vcc12 boot1 pwrok fbrtn_nb fbrtn fb comp ofs adj isn_nb isp_nb fb_nb comp_nb rt 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd 49 (top view) package type qw : wqfn-48l 7x7 (w-type) RT8868A lead plating system g : green (halogen free and pb free) marking information RT8868A gqw ymdnn RT8868Agqw : product number ymdnn : date code
RT8868A 2 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit 2 4 3 4 3 3 3 2 1 4 2 1 5 1 9 2 6 a d j v c c 5 r t u g a t e 1 i s n 1 r t 8 8 6 8 a i m a x l g a t e 1 9 3 5 b o o t 1 p w m 3 p h a s e 1 i s n 3 i s p 1 1 6 l 1 1 2 v i s p 3 2 0 p w m 4 2 5 n t c vcc pwm boot ugate phase lgate l 2 1 2 v 1 2 v gnd vcc pwm boot ugate phase lgate l 2 1 2 v 1 2 v gnd i s n 4 i s p 4 2 2 2 1 2 7 2 8 2 9 3 0 1 8 u g a t e 2 b o o t 2 i s p 2 p h a s e 2 i s n 2 1 7 l g a t e 2 l 2 1 2 v c o m p 1 1 f b 1 2 load c o m p _ n b 6 f b _ n b 5 3 6 3 7 3 8 3 9 7 u g a t e _ n b b o o t _ n b i s p _ n b p h a s e _ n b i s n _ n b 8 l g a t e _ n b l 2 1 2 v load v c c 1 2 3 1 1 2 v v c c 1 2 _ n b 4 0 1 2 v 1 3 i m a x _ n b 1 0 o f s 4 6 t o 4 1 v i d [ 5 : 0 ] 4 8 e n 1 p w r o k 4 7 p g o o d 3 4 f b r t n _ n b f b r t n r t 9 6 1 9 r t 9 6 1 9 r o f s p s 2 3 v c c p _ c o r e v c c p _ c o r e v c c p _ n b v c c p _ c o r e v c c p _ c o r e
RT8868A 3 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. 7-bit vid code table for am2+/am3 cpu (serial) svid[6:0] voltage svid[6:0] voltage svid[6:0] voltage svid[6:0] voltage 0000000 1.5500 0100000 1.1500 1000000 0.7500 1100000 0.3500 0000001 1.5375 0100001 1.1375 1000001 0.7375 1100001 0.3375 0000010 1.5250 0100010 1.1250 1000010 0.7250 1100010 0.3250 0000011 1.5125 0100011 1.1125 1000011 0.7125 1100011 0.3125 0000100 1.5000 0100100 1.1000 1000100 0.7000 1100100 0.3000 0000101 1.4875 0100101 1.0875 1000101 0.6875 1100101 0.2875 0000110 1.4750 0100110 1.0750 1000110 0.6750 1100110 0.2750 0000111 1.4625 0100111 1.0625 1000111 0.6625 1100111 0.2625 0001000 1.4500 0101000 1.0500 1001000 0.6500 1101000 0.2500 0001001 1.4375 0101001 1.0375 1001001 0.6375 1101001 0.2375 0001010 1.4250 0101010 1.0250 1001010 0.6250 1101010 0.2250 0001011 1.4125 0101011 1.0125 1001011 0.6125 1101011 0.2125 0001100 1.4000 0101100 1.0000 1001100 0.6000 1101100 0.2000 0001101 1.3875 0101101 0.9875 1001101 0.5875 1101101 0.1875 0001110 1.3750 0101110 0.9750 1001110 0.5750 110 1110 0.1750 0001111 1.3625 0101111 0. 9625 1001 111 0.5 625 1101111 0.1625 0010000 1.3500 0110000 0.9500 1010000 0.5500 1110000 0.1500 0010001 1.3375 0110001 0.9375 1010001 0.5375 1110001 0.1375 0010010 1.3250 0110010 0.9250 1010010 0.5250 1110010 0.1250 0010011 1.3125 0110011 0.9125 1010011 0.5125 1110011 0.1125 0010100 1.3000 0110100 0.9000 1010100 0.5000 1110100 0.1000 0010101 1.2875 0110101 0.8875 1010101 0.4875 1110101 0.0875 0010110 1.2750 0110110 0.8750 1010110 0.4750 1110110 0.0750 0010111 1.2625 0110111 0.8625 1010111 0.4625 111 0111 0.0675 0011000 1.2500 0111 000 0.8500 1011000 0.4500 1111000 0.0500 0011001 1.2375 0111 001 0.8375 1011001 0.4375 1111001 0.0375 0011010 1.2250 0111 010 0.8250 1011010 0.4250 1111010 0.0250 0011011 1.2125 0111011 0.8125 1011011 0.4125 1111011 0.0125 0011100 1.2000 0111100 0.8000 1011100 0.4000 1111100 off 0011101 1.1875 0111101 0.7875 1011101 0.3875 1111101 off 0011110 1.1750 0111110 0. 7750 1011110 0.3750 1111110 off 0011111 1.1625 0111111 0.7625 1 011111 0.3 625 1111 111 off
RT8868A 4 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. 6-bit vid code table for am2 cpu (parallel) vid[5:0] voltage vid[5:0] voltage vid[5:0] voltage vid[5:0] voltage 000000 1.5500 010000 1.1500 100000 0.7625 110000 0.5625 000001 1.5250 010001 1.1250 100001 0.7500 110001 0.5500 000010 1.5000 010010 1.1000 100010 0.7375 110010 0.5375 000011 1.4750 010011 1.0750 100011 0.7250 110011 0.5250 000100 1.4500 010100 1.0500 100100 0.7125 110100 0.5125 000101 1.4250 010101 1.0250 100101 0.7000 110101 0.5000 000110 1.4000 010110 1.0000 100110 0.6875 110110 0.4875 000111 1.3750 010111 0.9750 100 111 0. 6750 110111 0.4750 001000 1.3500 011000 0.9500 101000 0.6625 111000 0.4625 001001 1.3250 011001 0.9250 101001 0.6500 111001 0.4500 001010 1.3000 011010 0.9000 101010 0.6375 111010 0.4375 001011 1.2750 011011 0.8750 101011 0.6250 111011 0.4250 001100 1.2500 011100 0.8500 101 100 0.6125 111100 0.4125 001101 1.2250 011101 0.8250 101 101 0.6000 111101 0.4000 001110 1.2000 011110 0.8000 101110 0. 5875 11 1110 0.3875 001111 1.1750 011111 0.7750 101111 0. 5750 111111 0.3750
RT8868A 5 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 pwrok pwrok input signal. 2 rt connect this pin to gnd by a resistor to adjust frequency. 3 fbrtn remote sense ground for core. 4 fbrtn_nb remote sense ground for nb. 5 fb_nb inverting input of error-amp for nb. 6 comp_nb output of error-amp and input of pwm comparator for nb. 7 isp_nb positive current sense pin of nb. 8 isn_nb negative current sense pin of nb. 9 ad j connect this pin to gnd by a resistor to set load line of vcore. 10 ofs connect this pin to 5vcc by a resistor to set no-load offset voltage of v core . 11 comp output of error-amp and input of pwm comparator of v core . 12 fb inverting input of error-amp of v core . 13 imax_nb connect this pin to gnd by a resistor to set ocp of nb. 14 imax connect this pin to gnd by a resistor to set ocp of vcore. 15, 17, 19, 21 isn1, isn2, isn3, isn4 negative current sense pin of channel 1, 2, 3 and 4. 16, 18, 20, 22 isp1, isp2, isp3, isp4 positive current sense pin of channel 1, 2, 3 and 4. 23 ps power saving mode selection pin. 24 vcc5 output of internal 5v regulator for control circuits power supply. connect this pin to gnd by a ceramic capacitor larger than 1 f. 25,26 pwm4, pwm3 pwm output for channel 4 and channel 3. 27, 35, 36 boot2, boot1, boot_nb bootstrap supply for channel 2 and channel 1 and nb. 28, 34, 37 ugate2, ugate1, ugate_nb upper gate driver for channel 2 and channel 1 and nb. 29, 33, 38 phase2, phase1, phase_nb switching node of channel 2 and channel 1 and nb. 30, 32, 39 lgate2, lgate1, lgate_nb lower gate driver for channel 2 and channel 1 and nb. 31, 40 vcc12, vcc12_nb ic power supply. connect this pin to 12v. 41 vid0/vfixen pvi mode : used as voltage identification input for dac. svi mode : functions as vfixen selection input. 42 vid1/pvi this pin selects pvi/svi mode based on the state of this pin prior to en signal. pvi mode : used as voltage identification input for dac. 43 vid2/svd pvi mode : used as voltage identification input for dac. svi mode : serial data input. 44 vid3/svc pvi mode : used as voltage identification input for dac. svi mode : serial clock input. 45, 46 vid4, vid5 pvi mode : used as voltage identification input for dac. 47 pgood power good indicator (open drain). 48 en enable input signal. 49 (exposed pad) gnd reference ground for the ic. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8868A 6 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram vcc12 vcc5 boot1 ugate1 phase1 lgate1 boot2 ugate2 phase2 lgate2 pwm3 pwm4 isp1 isn1 isp2 isn2 isp3 isn3 isp4 isn4 adj fbrtn_nb vid5 to vid0 i_sen1 i_sen2 i_sen3 i_sen4 imax oc por por vidoff pwrok fb 1.8v ov comp oc ov rt 1.25v en ofs power-on reset 5v regulator mosfet driver mosfet driver ch3_en detector ch4_en detector ch1 current sense ch2 current sense ch3 current sense ch4 current sense avg vid table generator transient response enhancement soft start and fault logic transient response enhancement offset modulator waveform generator + - + - + - + - + - + + - + + - ea + - + - + - + - + - pgood fbrtn isp_nb isn_nb i_sennb nb current sense mosfet driver boot_nb ugate_nb phase_nb lgate_nb vcc12_nb + - ramp_nb - + ea fb_nb oc_nb imax_nb ov_nb - + + 1.8v comp_nb ps ramp_nb oc detection oc_nb detection
RT8868A 7 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit vcc supply input vcc12 supply voltage v vcc12 10.8 12 13.2 v vcc12 supply current i vcc12 -- 10 -- ma vcc12_nb supply voltage v vcc12_nb 10.8 12 13.2 v vcc12_nb supply current i vcc12_nb -- 5 -- ma vcc5 power vcc5 supply voltage v vcc5 i load = 10ma 4.9 5 5.1 v vcc5 output sourcing i vcc5 10 -- -- ma power on reset vcc12 rising threshold v vcc12th vcc12 rising 9.4 9.8 10.2 v vcc12 hysteresis v vcc12hy vcc12 falling -- 0.9 -- v recommended operating conditions (note 4) z supply voltage, vcc12 ----------------------------------------------------------------------------- 12v 10% z junction temperature range ----------------------- ------------------------------------------------ ? 40 c to 125 c z ambient temperature range ----------------------- ------------------------------------------------ ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage --------------------------------------------------------------------------------- ? 0.3v to 15v z bootx to phasex ---------------------------------------------------------------------------------- ? 0.3v to 15v z phasex to gnd dc -------------------------------------------------------------------------------------------------------- ? 2v to 15v <20ns --------------------------------------------------------------------------------------------------- ? 5v to 30v z ugatex to gnd dc -------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) <20ns --------------------------------------------------------------------------------------------------- (v phase ? 5v) to (v boot + 5v) z lgatex to gnd dc -------------------------------------------------------------------------------------------------------- (gnd ? 0.3v) to (v cc + 0.3v) <20ns --------------------------------------------------------------------------------------------------- (gnd ? 5v) to (v cc + 5v) z input/output voltage or i/o voltage -------------------------------------------------------------- ? 0.3v to 7v z power dissipation, p d @ t a = 25 c wqfn ? 48l 7x7 --------------------------------------------------------------------------------------- 3.226w z package thermal resistance (note 2) wqfn-48l 7x7, ja ---------------------------------------------------------------------------------- 31 c/w wqfn-48l 7x7, jc --------------------------------------------------------------------------------- 6 c/w z junction temperature -------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c z storage temperature range ----------------------- ------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) -------------------------------------- ----------------------------------- 2kv (v vcc12 = 12v, gnd = 0v, t a = 25 c, unless otherwise specified)
RT8868A 8 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit input threshold logic-high v enhi en rising 2 -- -- enable input threshold voltage logic-low v enlo en falling -- -- 0.8 v logic-high v pokhi pwrok rising 2 -- -- pwrok input threshold voltage logic-low v poklo pwrok falling -- -- 0.8 v vid5 to vid0 rising threshold v vid5 to 0 vid5 to vid0 rising 0.75 0.8 0.85 v vid5 to vid0 hysteresis v vid5 to 0 hys vid5 to vid0 falling -- 25 -- mv vid5 to vid0 pull-down current i vid 5 to 0 v vid5 to 0 = 1.5v -- 16 30 a reference voltage accuracy 1v to 1.55v ? 0.5 -- 0.5 % 0.8v to 1v ? 8 -- 8 mv dac accuracy 0.5v to 0.8v ? 10 -- 10 mv error amplifier dc gain a dc no load -- 80 -- db gain-bandwidth gbw c load = 10pf -- 10 -- mhz slew rate sr c load = 10pf 10 -- -- v/ s output voltage range v comp r load = 47k 0.5 -- 3.6 v power good over voltage threshold v pgood-ov fb rising v dac +210mv v dac +240mv v dac +270mv v under voltage threshold v pgood-uv fb falling v dac ? 330mv v dac ? 300mv v dac ? 270mv v over voltage threshold_nb v pgood-ov_nb fb_nb rising v dac +210mv v dac +240mv v dac +270mv v under voltage threshold_nb v pgood-uv_nb fb_nb falling v dac ? 330mv v dac ? 300mv v dac ? 270mv v power good low voltage v pgood i pgood = 4ma -- -- 0.4 v current sense amplifier max current i gm ma x v csp = 1.3v sink current from csn 100 -- -- a input offset voltage v oscs ? 2 0 2 mv oscillator running frequency f os c r rt = 40k 270 300 330 khz ramp amplitude v ramp -- 1.6 -- v soft-start soft-start slew rate sr ss slew rate 2.5 3.25 4 mv/ s vid change slew rate sr vid slew rate 2.5 3.25 4 mv/ s
RT8868A 9 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit protection v ovp sweep fb voltage 1.7 1.8 1.9 v over voltage threshold v ovp_nb sweep fb_nb voltage 1.7 1.8 1.9 v i ocp r imax = 40k 64.5 83 101.5 a v imax r imax = 40k 1.44 1.6 1.76 v i ocp_nb r imax_nb = 40k 64.5 83 101.5 a over-current threshold v imax_nb r imax_nb = 40k 1.44 1.6 1.76 v gate driver ugate drive source r ug atesr v boot ? v phase = 8v 250ma source current -- 1 -- ugate drive sink r ug atesk v boot ? v phase = 8v 250ma sink current -- 1 -- l gat e dri ve sourc e r lg atesr v lg ate = 8v -- 1 -- l gat e dri ve sink r lg atesk 250ma sink current -- 0.9 --
RT8868A 10 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics vid = 1.1v, i load = 6a time (200 s/div) power on from en_core en (2v/div) v ccp_core (1v/div) pgood (2v/div) ugate1 (20v/div) vid = 1.1v, i load = 6a time (200 s/div) power off from en_core en (2v/div) v ccp_core (1v/div) pgood (2v/div) ugate1 (20v/div) vid = 1.1v, i load = 6a time (200 s/div) power off from en_nb en (2v/div) v ccp_nb (1v/div) pgood (1v/div) ugate_nb (20v/div) vid = 1.1v, i load = 6a time (200 s/div) power on from en_svi mode en (2v/div) v ccp_nb (1v/div) pgood (2v/div) v ccp_core (1v/div) vid = 1.1v, i load = 6a time (200 s/div) power off from en_svi mode en (2v/div) v ccp_nb (1v/div) pgood (2v/div) v ccp_core (1v/div) vid = 1.1v, i load = 6a time (200 s/div) power on from en_nb en (2v/div) v ccp_nb (1v/div) pgood (1v/div) ugate_nb (20v/div)
RT8868A 11 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid = 0.8v, increase comp_nb voltage to trigger ovp time (40 s/div) over voltage protection_nb fb_nb (1v/div) ugate_nb (20v/div) lgate_nb (10v/div) vid = 0.8v, increase comp voltage to trigger ovp time (40 s/div) over voltage protection_core fb (1v/div) ugate1 (20v/div) lgate1 (10v/div) time (100 s/div) over current protection_nb i load (20a/div) v ccp_nb (1v/div) pgood (1v/div) ugate_nb (20v/div) time (100 s/div) over current protection_core i load (50a/div) v ccp_core (1v/div) pgood (1v/div) ugate1 (20v/div) time (40 s/div) dynamic vid down svc (2v/div) v ccp_nb (1v/div) v ccp_core (1v/div) svd (2v/div) time (40 s/div) dynamic vid up svc (2v/div) v ccp_nb (1v/div) v ccp_core (1v/div) svd (2v/div)
RT8868A 12 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. load transient response_nb time (20 s/div) i load = 20a to 5a v ccp_nb (100mv/div) i load 5a 20a -> 1.1v load transient response_core time (20 s/div) i load = 30a to 90a i load 30a 90a v ccp_core (100mv/div) -> 1.1v load transient response_core time (20 s/div) i load = 90a to 30a v ccp_core (100mv/div) i load 30a 90a -> 1.1v load transient response_nb time (20 s/div) i load = 5a to 20a v ccp_nb (100mv/div) i load 5a 20a -> 1.1v
RT8868A 13 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 1. svi communication-send byte application information the RT8868A is a dual output pwm controller that supports hybrid power control of amd processors which operate from either a 6-bit parallel vid interface (pvi) or a serial vid interface (svi). one of the outputs is a 4/3/2/1-phase pwm controller with two integrated mosfet drivers to support cpu core voltage (vdd) and another is a single- phase buck controller with an integrated mosfet driver to power north-bridge (nb) chipset (vddnb) in svi mode. in pvi mode, only multiphase pwm controller is active for single plane vdd only processor. richtek's proprietary burst transient response(btr tm ) provides fast initial response to high di/dt load transients and requires less bulk and ceramic output capacitance to meet transient regulation specifications. the RT8868A incorporates differential voltage sensing, continuous inductor dcr phase current sensing, programmable load- line voltage positioning and offset voltage to provide high accuracy regulated power for both vdd and vddnb. while vddnb is enabled in svi mode, it will be automatically phase-shifted with respect to the cpu core phases in order to reduce the total input rms current amount. cpu_type detection and system start-up at system start-up, on the rising-edge of en signal, the RT8868A monitors the status of vid1 and latches the pvi mode (vid1 = 1) or svi mode (vid1 = 0). pvi mode pvi is a 6-bit-wide parallel interface used to address the cpu core section reference. according to the selected code, the device sets the core section reference and regulates its output voltage according to table 2. in this mode, nb section is kept in high impedance. furthermore, pwrok information is ignored as well since the signal only applies to the svi protocol. svi mode svi is a two wire, clock and data, bus that connects a single master (cpu) to one slave (RT8868A). the master initiates and terminates svi transactions and drives the clock, svc, and the data, svd, during a transaction. the slave receives the svi transactions and acts accordingly. svi wire protocol is based on fast-mode i 2 c as shown in figure 1. svi interface also considers two additional signals needed to manage the system start-up. these signals are en and pwrok. the device asserts a pgood signal if the output voltages are in regulation. set vid command the set vid command is defined as the command sequence that the cpu issues on the svi bus to modify the voltage level of the core section and nb section, as shown is figure 1. during a set vid command, the processor sends the start (start) sequence followed by the address of the section which the set vid command applies. the processor then sends the write (write) bit. after the write bit, the voltage regulator (vr) sends the acknowledge (ack) bit. the processor then sends the vid bits code during the data phase. the vr sends the acknowledge (ack) bit after the data phase. finally, the processor sends the stop (stop) sequence. after the vr has detected the stop, it performs an on-the-fly vid transition for the addressed section(s). refer to table 3 for the details of svi send byte. the RT8868A is able to manage individual power off for both vcore and nb sections. the cpu may issue a serial vid command to power off or power on one section while the other one remains powered. in this cas e, the pgood signal remains asserted. start slave addressing + w ack ack data phase stop svc svd start slave addressing (7 clocks) write (1ck) ack (1ck) data phase (8 clocks) ack (1ck) stop bus driven by RT8868A bus driven by master (cpu) 65430 760 110b ack ack
RT8868A 14 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. bits description address phase 6 : 4 always 110b 3 not applicable, ignored. 2 not applicable, ignored. 1 core section. (note) if set then the following data byte contains the vid code for core section. 0 nb section. (note) if set then the following data byte contains the vid code for nb section. data phase 7 psi_l flag (active low). when asserted, the vr is allowed to enter power-saving mode. 6 : 0 vid code. table 3. svi send byte-address and data phase description / example note : assertion in both bit 1 and 0 will address the vid code to both core and nb simultaneously. pwrok de-assertion pwrok stays low after en signal is asserted, and the controller regulates all the planes according to the pre- pwrok metal vid. pgood is de-asserted as long as pre-pwrok metal vid voltage is out of the initial voltage specifications. v_fix mode function anytime the pin vid0/vfixen is pulled high, the controller enters v-fix mode. when in v_fix mode, both vcore and nb section voltages are governed by the information shown in table 4. regardless of the state of pwrok, the device will work in svi mode. svc and svd are considered as static vid and the output voltage will be changed according to their status. dynamic svc/svd-change management is provided in this condition. v_fix mode is intended for system debug only. table 4. v_fix mode and pre-pwrok metal vid output voltage (v) svc svd pre-pwrok metal vid v_fix mode 0 0 1.1v 1.4v 0 1 1.0v 1.2v 1 0 0.9v 1.0v 1 1 0.8v 0.8v example : svi address bits [6 : 0] description 1100_000 should be ignored. 1100_001 set vid on vddnb. 1100_110 set vid on vdd0 and vdd1. 1100_100 set vid on vdd1. 1100_010 set vid on vdd0 or vdd (uniplane). 1100_111 set vid on vddnb, vdd0 and vdd1. power ready detection during start-up, the RT8868A will detect vcc12, vcc5 and en signal. figure 2 shows the power ready detection circuit. when vcc12 > 9.6v a nd vcc5 > 4.6v, por (power on reset) will go high. por is the internal signal to indicate all input powers are ready to allow the RT8868A and the companioned mosfet drivers to work properly. when por = l, the RT8868A will turn off both high side and low side mosfets. figure 2. circuit for power ready detection power-up sequencing figure 3 and 4 are the power-up sequencing diagram of the RT8868A. once power_on_reset is valid (por = h), on the rising edge of the en signal, the RT8868A detects the vid1 pin and determines whether to operate in svi or pvi mode. figure3 shows the pvi-mode power sequence, the controller stays in t1 state waiting for valid parallel vid code sent by cpu. after receiving valid parallel vid code, vcore continues ramping up to the specified voltage according to the vid code in t2 state. figure 4 shows the svi-mode power sequence, the controller samples the two serial vid pins, svc and svd. then, the controller stores this value as the boot vid that is the so-called ? pre-pwrok metal vid ? in t1 state. after the processor starts with boot vid voltages, pwrok is asserted and the processor initializes the serial vid interface in t2 state. the processor uses the serial vid interface to issue vid commands to move the power planes from the boot vid values to the dual power planes in t3 state. por vcc12 en + - cmp + - cmp 9.6v 4.6v vcc5 chip enable
RT8868A 15 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6. r rt vs. phase switching frequency figure 3. pvi-mode power-sequencing diagram figure 4. svi-mode power-sequencing diagram core section output current sensing the RT8868A provides a low input offset current sense amplifier (csa) to monitor the continuous output current of each phase for v core . output current of csa (i x [n]) is used for current balance and active voltage position as shown in figure 5. in this inductor current sensing topology, r s and c s must be set according to the equation below : then the output current of csa will follow the equation below : 235na is the typical value of the csa input offset current. v ofs-csa is the input offset. usually, ? v ofs-csa + 235na x (r csp ? r csn ) ? is negligible except at very light load and the equation can be simplified as the equation below : figure 5. current sensing circuit core section phase detection the number of the operational phases is determined by the internal circuitry that monitors the isnx voltages during start up. normally, the RT8868A operates as a 4-phase pwm controller. pull isn4 and isp4 to 5vcc programs 3-phase operation, pull isn3 and isp3 to 5vcc programs 2-phase operation, and pull isn2 and isp2 to 5vcc programs 1-phase operation. the RT8868A detects the voltage of isn4, isn3 and isn2 at rising edge of por. at the rising edge, the RT8868A detects whether the voltage of isn4, isn3 and isn2 are higher than ? vcc5-1v ? respectively to decide how many phases should be active. phase detection is only active during start up. once por = high, the number of operational phases is determined and latched. core section switching frequency connecting a resistor (r rt ) from the rt pin to gnd programs the switching frequency of each phase. figure 6 shows the relationship between the resistance and switching frequency. en vcc5 svc vdd or vddnb pgood por vboot vcc12 xx pwrok vid(1)/pvi xx valid svd xx valid t1 t2 t3 9.6v 4.6v 8.7v 4.2v en vcc5 vdd pgood por vcc12 8.7v pwrok vid(1)/pvi xx pvi mode (6-bits) valid xx t1 t2 4.2v 9.6v 4.6v ss l rc dcr = lofs-csa cspcsn x csn [i dcr v 235na (r r )] i r ? + ? = l x csn i dcr i r = + - 235na 235na v ofs_csa + - isn isp r csp r csn r s dcr c s l i x csa: current sense amplifier 0 200 400 600 800 1000 1200 0 40 80 120 160 200 240 280 r rt (k ohm) frequency (khz ) (k )
RT8868A 16 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 8. load transient quick response core section current balance in figure 9, i x [n] is the current signal which is proportional to the current flowing through channel n. the current error signals i err [n] ( = i x [n] ? avg(i x [n])) are used to raise or lower the valley of internal sawtooth waveforms (eamp[1] i out v out fb = v eap = v eap - v qr fb qr + - + - fb comp qr eap - v qr eap = v dac - v adj c1 c2 r1 r fb c fb v out core section differential output voltage sensing the RT8868A uses differential voltage sensing by a high gain low offset error-amp as shown in figure 7. connect the negative on-die cpu remote sense pin to fbrtn. connect the positive on-die remote sense pin to fb with a resistor (r fb ) the error-amp compares eap ( = v dac ? v adj ) with v fb to regulate the output voltage. core section programmable load-line output current of csa is summed and averaged in the RT8868A. then 0.5 (i x [n]) is sent to adj pin. because i x [n] is a ptc (positive temperature coefficient) current, an ntc (negative temperature coefficient) resistor is needed to connect adj pin to gnd. if the ntc resistor is properly selected to compensate the temperature coefficient of i x [n], the voltage on adj pin will be out adj adj out out csn vv r 1 ll(loadline) dcr ii2r ? === ? briefly, the resistance of r adj sets the resistance of loadline. the temperature coefficient of r adj compensates the temperature effect of loadline. core section load transient quick response in steady state, the value of v fb is controlled to be very close to v eap . however, a load step transient from light load to heavy load can still cause v fb to become lower than v eap by several tens of mv. in prior design, owing to limited control bandwidth, it is difficult for the controller to prevent v out undershoot during quick load transient from light load to heavy load. the RT8868A has a built-in proprietary burst transient response (btr tm ) technology that detects load transient by comparing v fb and v eap . if v fb suddenly drops below ? v eap ? v qr ? ( v qr is a predetermined voltage), the quick response indicator qr rises up. when qr = high, the RT8868A turns on all high side mosfets and turns off all low side mosfets. the sensitivity of quick response can be adjusted by the values of c fb and r fb . smaller r fb and/or larger c fb will make qr easier to be triggered. figure 8 illustrates the circuit and typical waveforms. figure 7. circuit for vcore differential sensing and no load offest proportional to i out without temperature effect. in the RT8868A, the positive input of error-amp is ? v dac ? v adj ? . v out will follow ? v dac ? v adj ? , too. thus, the output voltage which decreases linearly with i out is obtained. the loadline is defined as : =? = ? ofsp ofsp fb adj fb a dj ofs vir9 r r 0.4 9 r r core section no-load offset in figure 7, i ofsp is used to generate no-load offset. connect a resistor from ofs pin to 5vcc to activate i ofsp . i ofsp flows through r fb from the v ccp to fb pin. in this case, positive no-load offset voltage (v ofsp ) is generated. besides i ofsp , the RT8868A generates another dc current for initial no-load negative offset. a dc current source will continuously inject typical 9 a current into the resistors connected to adj pin, therefore, the effect of this 9 a current source and adj resistors should be included in the calculation of no-load offset : fb c fb r fb v ccp (positive remote sense pin of cpu) + - ea + - v dac + - eap comp fbrtn adj c1 c2 r1 v ccn (negative remote sense pin of cpu) r adj i ofsp
RT8868A 17 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. once i x is larger than 2 x i imax , the ocp of core section is triggered and latched. then, the RT8868A will turn off both high side mosfet and low side mosfet of all channels. a 100 s delay is used in ocp detection circuit to prevent false trigger. except the normal ocp function described above, there is another short circuit ocp function especially designed for short circuit protection. since short circuit may cause catastrophic damage over a very short period, the short circuit ocp should have a very short delay for triggering ocp latch. also to prevent false trigger, the trigger level imax x(max) imax x(max) imax imax csnx csnx imax lx(max) x(max) ximaxx 11 ii 48 v i2i2 r rr v ii 2 dcr r dcr = = = = = core section phase current adjustment if phase current is not balanced due to asymmetric pcb layout of power stage, external resistors can be adjusted to correct current imbalance. figure10 shows two types of current imbalance, constant ratio type and constant difference type. if the initial current distribution is constant ratio type, according to equation (3), reducing r csn [1] can reduce i l [1] and improve current balance. if the initial current distribution is constant difference type, according to equation (2), increasing r csp [1] can reduce i l [1] and improve current balance. core section over current protection (ocp) core section uses an external resistor r imax connected to imax pin to generate a reference current i max for over current protection as depicted in figure 11. where v imax is typically 1.6v. the RT8868A senses each phase current i x and the ocp comparator compares sensed average current with the reference current. equivalently, the maximum phase average current i lx(max) is calculated as below : figure 9. circuit channel current balance + - + - + - + - comp i err [1] x r cb i err [n] x r cb interleaved ramp[1] ramp[n] cmp cmp buf buf pwm[1] pwm[n] constant ratio i out , total i1 i2 constant difference i out , total i1 i2 figure 10. category of phase current imbalance imax imax imax v i r = figure 11. over current protection for core section to ramp[n]) which is compared with error-amp output (comp) to generate pwm signal. raising the valley of sawtooth waveform will decrease the pwm duty of the corresponding channel, while lowering the sawtooth waveform valley will increase the pwm duty. eventually, the current flowing through each channel will be balanced. r csnx r x dcr x c x l x ocp comparator pwm controller v in hs ls + - i x + - 8 4 1/8i x 1/4i imax i imax + - 1.6v i lx gm r imax RT8868A core section v imax
RT8868A 18 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. and the delay of short circuit ocp of nb section is 20 s. when short circuit ocp is triggered at nb section, the RT8868A will turn off both high side mosfet and low side mosfet of nb section. core section over voltage protection (ovp) the over voltage protection monitors the output voltage via the fb pin. once v fb exceeds 1.8v, ovp is triggered and latched for vcore section. RT8868A will try to turn on each low side mosfet and turn off each high side mosfet to protect cpu. , csnx imax lx(max), short lx(max) imax x r v i = 1.5 x i = 3 r dcr and the delay of short circuit ocp is 20 s. when short circuit ocp is triggered, the RT8868A will turn off both high side mosfet and low side mosfet of all channels. nb s_nb s_nb nb l rc dcr = then the output current of csa will follow the equation below : l_nb nb x_nb csn_nb i dcr i r = nb section output current sensing the RT8868A provides low input offset current sense amplifier (csa) to monitor the continuous output current of nb section. output current of csa (i x_nb ) is used for over current detection as shown in figure 12. in this inductor current sensing topology, r s_nb and c s_nb must be set according to the equation below : r csn_nb r s_nb dcr nb c s_nb l nb i x_nb csa: current sense amplifier + - figure 12. current sensing circuit for nb section nb section over current protection (ocp) nb section uses an external resistor r imax_nb connected to imax_nb pin to generate a reference current i max_nb for over current protection as depicted in figure 13. imax_nb imax_nb imax_nb v i r = where v imax_nb is typically 1.6v. the ocp comparator compares the sensed phase current i x_nb with the reference current. equivalently, the maximum phase nb current i lx_nb(max) is calculated as below : imax_nb x_nb imax_nb x_nb imax_nb imax_nb csn_nb lx_nb(max) x_nb nb imax_nb csn_nb imax_nb nb 11 ii 48 v i2i 2 r r ii dcr vr 2 rdcr = = = = = once i x_nb is larger than 2 x i imax_nb , ocp of nb section is triggered and latched. then, the RT8868A will turn off both high side mosfet and low side mosfet of nb section. a 100 s delay is used in ocp detection circuit to prevent false trigger. except the normal ocp function described above, there is another short circuit ocp function especially designed for short circuit protection. since short circuit may cause catastrophic damage over a very short period, the short circuit ocp should have a very short delay for triggering ocp latch. also to prevent false trigger, the trigger level of the short circuit ocp is designed 1.5 times of normal ocp level of nb section. hence, the equation of nb section short circuit ocp threshold is : , lx_nb(max), short lx_nb(max) imax_nb csn_nb nb imax_nb i = 1.5 x i vr = 3 rdcr of the short circuit ocp is designed 1.5 times of normal ocp level. hence, the equation of short circuit ocp threshold is :
RT8868A 19 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. nb section over voltage protection (ovp) the over voltage protection monitors the output voltage via the fb_nb pin. once v fb_nb exceeds 1.8v, ovp is triggered and latched for nb section. the RT8868A will try to turn on low side mosfet and turn off high side mosfet to protect nb. power saving indicator (psi) this is an active low flag that can be set by the cpu to allow the regulator to enter power-saving mode to maximize the system efficiency when in light-load conditions. the status of the flag is communicated to the controller through either the svi bus or ps pin. the RT8868A monitors the ps pin to define the action performed by the controller when psi is asserted. according to figure 14, by programming different voltage on ps pin, this configures the controller to operate in one or two-phase condition when psi is asserted. by pulling up ps pin to 3.3v through a resistor, the controller operates in only one-phase configuration. if the 3.3v is changed to 5v, the RT8868A operates in two-phase configuration. when psi is de-asserted, the controller will return to the original configuration. the psi strategy is summarized as shown in table 5. figure 14. power-saving-mode circuit table 5. psi strategy ps pin psi strategy pull-up to 3.3v phase number is set to 1 while psi is asserted. pull-up to 5v phase number is set to 2 while psi is asserted. latch psoc2p en control psia psi (from i2c) psi (active low) vddio (1) 5vcc for (4 phase to 2 phase) (2) 3.3v for (4 phase to 1 phase) 5vcc ps figure 13. over current protection for nb section non-overlap control of mosfet driver to prevent the overlap of the gate drives during the ugate pull low and the lgate pull high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to pull low (after propagation delay). before lgate can pull high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1v. once the monitored voltages fall below 1.1v, lgate begins to turn high. by waiting for the voltages of the phase pin and high side gate drive to fall below 1.1v, the non-overlap protection circuit ensures that ugate is low before lgate pulls high. also to prevent the overlap of the gate drives during lgate pull low and ugate pull high, the non-overlap circuit monitors the lgate voltage. when lgate go below 1.1v, ugate goes high after propagation delay. layout considerations careful pcb layout is critical to achieve low switching losses and clean, stable operation. the high power switching power stage requires particular attention. follow these guidelines for optimum pcb layout. r csn_nb r x_nb dcr nb c x_nb l x_nb ocp comparator pwm controller v in hs ls + - i x_nb + - 8 4 1/8i x_nb 1/4i imax_nb i imax_nb + - 1.6v i lx gm r imax_nb RT8868A nb section v imax_nb
RT8868A 20 ds8868a-00 may 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 15. derating curve of maximum power dissipation 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb place the power components first, including power mosfets, input and output capacitors, and inductors. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. great attention should be paid for routing the ugate, lgate, and phase traces since they drive the power train mosfets with short, high current pulses. it is important to size them as large and short as possible to reduce their overall impedance and inductance. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot through. when placing the mosfets, try to keep the source of the upper mosfets and the drain of the lower mosfets as close to each other as possible. input bulk capacitors should be placed close to the drain of the upper mosfets and the source of the lower mosfets. locate the output inductors and output capacitors between the mosfets and the load. route high-speed switching nodes away from sensitive analog areas (isp, isn, fb, fbrtn, comp, adj, ofs, imax.....) keep the routing of the bootstrap capacitor short between boot and phase. place the snubber r&c as close as possible to the lower mosfets of each phase. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-48l 7x7 package, the thermal resistance, ja , is 31 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (31 c/w) = 3.226w for wqfn-48l 7x7 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 15 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT8868A 21 ds8868a-00 may 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 6.950 7.050 0.274 0.278 d2 5.050 5.250 0.199 0.207 e 6.950 7.050 0.274 0.278 e2 5.050 5.250 0.199 0.207 e 0.500 0.020 l 0.350 0.450 0.014 0.018 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options w-type 48l qfn 7x7 package

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